utron ut6164c rev. 1.0 8k x 8 bit high speed cmos sram utron technology inc. p80074 1f, no. 11, r&d rd. ii, science-based industr ial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 1 ? features fast access time : 10/12/15 ns (max.) low operating power consumption : 80 ma (typical) single 5v power supply all inputs and outputs ttl compatible fully static operation three state outputs package : 28-pin 300 mil soj 28-pin 8mm13.4mm stsop functional block diagram memory array 128 rows x 512 columns column i/o column decoder row decoder i/o control logic control a4 i/o1 v ss v cc we oe 1 ce i/o8 . . . . . . . . . a5 a 6 a 7 a 8 a11 a12 a 9 a 3 a 2 a 1 a 0 a 10 . . . . . . ce2 pin description symbol description a0 - a12 address inputs i/o1 - i/o8 data inputs/outputs 1 ce ce2 chip enable input we write enable input oe output enable input v cc power supply v ss ground general description the ut6164c is a 65,536-bit high-speed cmos static random access memory organized as 8,192 words by 8 bits. it is fabricated using high performance, high reliability cmos technology. the ut6164c is designed for high-speed system applications. it is particularly suited for use in high-density high-speed system applications. the ut6164c operates from a single 5v power supply and all inputs and outputs are fully ttl compatible. pin configuration a12 a7 a6 a5 a4 a3 a2 a1 a0 i/o1 i/o2 vcc a8 a9 a11 a10 i/o8 i/o7 i/o6 i/o5 i/o4 i/o3 vss ut6164c soj 28 14 13 12 11 10 9 8 7 6 5 4 3 2 1 17 16 15 20 19 18 22 23 24 25 26 27 21 we oe ce2 nc ce1 i/o4 a11 a9 a8 ce2 i/o3 a10 nc a12 a7 a6 a5 vcc i/o8 i/o7 i/o6 i/o5 vss i/o2 i/o1 a0 a1 a2 a4 a3 ut6164c stsop 28 14 13 12 11 10 9 8 7 6 5 4 3 2 1 17 16 15 20 19 18 22 23 24 25 26 27 21 we oe ce1
utron ut6164c rev. 1.0 8k x 8 bit high speed cmos sram utron technology inc. p80074 1f, no. 11, r&d rd. ii, science-based industr ial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 2 ? absolute maximum ratings * parameter symbol rating unit terminal voltage with respect to vss v term -0.5 to +6.5 v operating temperature t a 0 to +70 storage temperature t stg -65 to +150 power dissipation p d 1 w dc output current i out 50 ma soldering temperature (under 10 sec) tsolder 260 *stress greater than those listed under ?absolute maximum rati ngs? may cause permanent damage to the device. this is a stress rating only and functional operation of the devic e or any other conditions above those indicated in the operat ional sections of this specification is not implied. exposure to the absolute maximum rating conditions for extended period may affect device reliability. truth table mode 1 ce ce2 oe we i/o operation supply current standby h x x x high - z i sb , i sb1 standby x l x x high - z i sb , i sb1 output disable l h h h high - z i cc read l h l h d out i cc write l h x l d in i cc note: h = v ih , l=v il , x = don't care. dc electrical characteristics (v cc = 5v 10%, t a = 0 to 70 ) parameter symbol test condition min. max. unit input high voltage v ih 2.2 v cc +0.5 v input low voltage v il - 0.5 0.8 v input leakage current i li v ss Q v in Q v cc - 1 1 a output leakage current i lo v ss Q v i/o Q v cc 1 ce =v ih or ce2=v il or oe =v ih or we =v il - 1 1 a output high voltage v oh i oh = - 4ma 2.4 - v output low voltage v ol i ol = 8ma - 0.4 v - 10 - 180 ma - 12 - 160 ma operating power supply current i cc cycle time=min. 1 ce = v il , ce2= v ih i i/o = 0ma - 15 - 140 ma standby current (ttl) i sb 1 ce = v ih or ce2= v il - 30 ma standby current (cmos) i sb1 1 ce R v cc -0.2v or ce2 Q 0.2v - 5 ma
utron ut6164c rev. 1.0 8k x 8 bit high speed cmos sram utron technology inc. p80074 1f, no. 11, r&d rd. ii, science-based industr ial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 3 ? capacitance (t a =25 , f=1.0mhz) parameter symbol min. max. unit input capacitance c in - 8 pf input/output capacitance c i/o - 10 pf note : these parameters are guaranteed by device characterization, but not production tested. ac test conditions input pulse levels 0v to 3.0v input rise and fall times 3ns input and output timing reference levels 1.5v output load c l =30pf, i oh /i ol =-4ma/8ma ac electrical characteristics (v cc = 5v 10% , t a = 0 to 70 ) (1) read cycle ut6164c-10 ut6164c-12 ut6164c-15 unit parameter symbol min. max. min. max. min. max. read cycle time t rc 10 - 12 - 15 - ns address access time t aa - 10 - 12 - 15 ns chip enable access time t ace - 10 - 12 - 15 ns output enable access time t oe - 5 - 6 - 7 ns chip enable to output in low z t clz* 2 - 3 - 4 - ns output enable to output in low z t olz* 0 - 0 - 0 - ns chip disable to output in high z t chz* - 5 - 6 - 7 ns output disable to output in high z t ohz* - 5 - 6 - 7 ns output hold from address change t oh 3 - 3 - 3 - ns (2) write cycle ut6164c-10 ut6164c-12 ut6164c-15 unit parameter symbol min. max. min. max. min. max. write cycle time t wc 10 - 12 - 15 - ns address valid to end of write t aw 8 - 10 - 12 - ns chip enable to end of write t cw 8 - 10 - 12 - ns address set-up time t as 0 - 0 - 0 - ns write pulse width t wp 8 - 9 - 10 - ns write recovery time t wr 0 - 0 - 0 - ns data to write time overlap t dw 6 - 7 - 8 - ns data hold from end of write time t dh 0 - 0 - 0 - ns output active from end of write t ow* 2 - 3 - 4 - ns write to output in high z t whz* - 6 - 7 - 8 ns *these parameters are guaranteed by device char acterization, but not production tested.
utron ut6164c rev. 1.0 8k x 8 bit high speed cmos sram utron technology inc. p80074 1f, no. 11, r&d rd. ii, science-based industr ial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 4 ? timing waveforms read cycle 1 (address controlled) (1,2,4) t rc address dout data valid t aa t oh t oh read cycle 2 ( 1 ce ce2 and oe controlled) (1,3,5,6) t rc t aa t ace1 t ace2 t oe t chz1 t chz2 t ohz t clz1 t clz2 t oh t olz high-z data valid high-z address ce1 ce2 oe dout notes : 1. we is high for read cycle. 2. device is continuously selected 1 ce =v il and ce2=v ih. 3. address must be valid prior to or coincident with 1 ce and ce2 transition; otherwise t aa is the limiting parameter. 4. oe is low. 5. t clz1 , t clz2 , t olz , t chz1 , t chz2 and t ohz are specified with c l =5pf. transition is measured 500mv from steady state. 6. at any given temperature and voltage condition, t chz1 is less than t clz1 , t chz2 is less than t clz2 , t ohz is less than t olz.
utron ut6164c rev. 1.0 8k x 8 bit high speed cmos sram utron technology inc. p80074 1f, no. 11, r&d rd. ii, science-based industr ial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 5 ? write cycle 1 ( we controlled) (1,2,3,5) t wc t aw t cw1 t as t wp t wh t ow t dw t dh t cw2 t wr address ce1 ce2 we dout din data valid high-z (4) (4) write cycle 2 ( 1 ce ce2 controlled) (1,2,5) t wc t aw t cw1 t as t wr t cw2 t wp t whz t dw t dh data valid address ce1 ce2 we dout din high-z notes : 1. we or 1 ce must be high or ce2 must be low during all address transitions. 2. a write occurs during the overlap of a low 1 ce , a high ce2 and a low we . 3. during a we controlled with write cycle with oe low, t wp must be greater than t whz +t dw to allow the i/o drivers to turn off and data to be placed on the bus. 4. during this period, i/o pins are in the output state, and input singals must not be applied. 5. if the 1 ce low and ce2 high transition occurs simultaneously with or after we low transition, the outputs remain in a high impedance state. 6. t ow and t whz are specified with c l =5pf. transition is measured 500mv from steady state.
utron ut6164c rev. 1.0 8k x 8 bit high speed cmos sram utron technology inc. p80074 1f, no. 11, r&d rd. ii, science-based industr ial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 6 ? package outline dimension 28 pin 300 mil soj package outline dimension 1 28 14 15 a2 l c xx x note: 1. s/e/d dim not includeing mold flash. 2. the end flash in package lengthwise is not more than 10 mils each side unit symbol inch(base) mm(ref) a 0.148 (max) 3.759 (max) a1 0.026(min) 0.660(min) a2 0.100 0.005 2.540 0.127 b 0.018 (typ) 0.457(typ) b1 0.028 (typ) 0.711(typ) c 0.010 (typ) 0.254 (typ) d 0.710 (typ) 18.034 (typ) e 0.335(typ) 8.509(typ) e1 0.3 (typ) 7.620(typ) e 0.050 (typ) 1.270 (typ) l 0.087 0.010 2.210 0.254 s 0.030 (typ) 0.762 (typ) y 0.003(max) 0.076(max) d
utron ut6164c rev. 1.0 8k x 8 bit high speed cmos sram utron technology inc. p80074 1f, no. 11, r&d rd. ii, science-based industr ial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 7 ? 28 pin 8x13.4mm stsop package outline dimension 1 14 15 28 c l hd d "a" b e e 12 (2x) 12 (2x) seating plane y 28 15 14 1 c a2 a1 l a 0.254 0 gauge plane 12 (2x) 12 (2x) seating plane "a" datail view l1 note e dimension is not including end flash the total of both sides? end flash is not above 0.3mm. unit symbol inch(base) mm(ref) a 0.047 (max) 1.20 (max) a1 0.004 0.002 0.10 0.05 a2 0.039 0.002 1.00 0.05 b 0.008 0.001 0.200 0.025 c 0.005 (typ) 0.127(typ) db 0.465 0.004 11.80 0.10 e 0.315 0.004 8.00 0.10 e 0.022 (typ) 0.55(typ) d 0.528 0.008 13.40 0.20 l 0.0236 0.004 0.50 0.10 l1 0.0315 0.004 0.80 0.10 y 0.003(max) 0.076(max) 0 o ? 5 o 0 o ? 5 o h h c h f c
utron ut6164c rev. 1.0 8k x 8 bit high speed cmos sram utron technology inc. p80074 1f, no. 11, r&d rd. ii, science-based industr ial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 8 ? ordering information part no. access time (ns) package UT6164CJC-10 10 28 pin soj ut6164cjc-12 12 28 pin soj ut6164cjc-15 15 28 pin soj ut6164cls-10 10 28 pin stsop ut6164cls-12 12 28 pin stsop ut6164cls-15 15 28 pin stsop
utron ut6164c rev. 1.0 8k x 8 bit high speed cmos sram utron technology inc. p80074 1f, no. 11, r&d rd. ii, science-based industr ial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 9 ? revision history revision description date rev. 1.0 original oct 15,2001
utron ut6164c rev. 1.0 8k x 8 bit high speed cmos sram utron technology inc. p80074 1f, no. 11, r&d rd. ii, science-based industr ial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 10 ? this page is left blank intentionally.
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